Rambus announces PCIe 6.0: Powering high-performance data center and next-generation AI solutions

Rambus has just announced its all-new PCIe 6.0 interface subsystem that will reach its next generation data center and AI solutions.

Rambus provides a PCIe 6.0 interface subsystem for high-performance data centers and AI SoCs

Press release: Rambus Inc. announced. (NASDAQ: RMBS), the leading provider of chips and a silicon IP provider that makes data faster and more secure, today announced the availability of its PCI Express® (PCIe®) 6.0 subsystem consisting of a PHY and an IP controller. Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link (CXL) specification, version 3.0.

“Rapid advances in artificial intelligence/machine learning and data-intensive workloads are driving the continued evolution of data center architectures that require higher levels of performance,” said Scott Hutton, general manager of Interface IP at Rambus. “The Rambus PCIe 6.0 interface subsystem supports the performance requirements of next-generation data centers with the best latency, power, space, and security.”

The Rambus PCIe 6.0 interface subsystem delivers data transfer rates of up to 64 gigabits per second (GT/s) and is fully optimized to meet the needs of advanced heterogeneous computing architectures. Within the subsystem, the PCIe controller features a Data Encryption and Integration Engine (IDE) dedicated to protecting PCIe links and valuable data transmitted through them. On the PHY side, there is full support for CXL 3.0 to enable chip-level solutions for sharing, expanding, and aggregating coherent memory for caching.

PCI Express layer

  • Designed for the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32 and 64 and 128 bits)
  • SerDes Architecture PIPE 10b/20b/40b/80b . supports display
  • Supports native PIPE display 8b/16b/32b/64b/128b
  • Compliant with SR-IOV specification for PCI-SIG Single-Root I/O
  • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
  • Supports endpoint, root port, dual mode, switch port configurations
  • Supports PCIe 6.0 to PCIe 1.0 . speeds
  • Supports Forward Error Correction (FEC) – a lightweight algorithm for low latency
  • Supports L0p المنخفضة Low Power Mode
  • Up to 4-bit parity protection for the data path
  • Supports clock gate and energy gate
  • RAS features include LTSSM timer bypass, ACK/NAK/Replay/UpdateFC timer bypass, unencrypted access to the PIPE interface, error input on Rx and Tx paths, detailed recovery status, and much more, allowing for secure and reliable IP deployment on missions Critical SoCs

“PCIe is ubiquitous in the data center and CXL will become increasingly important as companies seek increased speeds and bandwidth to support higher levels of performance in next-generation applications,” said Shane Rao, Vice President of Research, IDC Semiconductor Computing. “With an increasing number of chip companies emerging to support new data center architectures, access to high-performance interface IP solutions will be fundamental to enabling the ecosystem.”

The main features of the Rambus PCIe 6.0 interface subsystem include:

  • Supports PCIe 6.0 specifications including 64 GT/s data rate and PAM4 signals
  • It performs forward error correction (FEC) with low latency of link strength
  • Supports fixed-size FLITs that enable high bandwidth efficiency
  • Backward compatible with PCIe 5.0, 4.0 and 3.0 / 3.1

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